Dsch 3.1 Software Software On 65Nm

International Journal of Computer Trends and Technology (IJCTT) V50(2):101-106, August 2017.

Design of power efficient counter design has become essential for the researchers.

In leakage dominant technologies, leakage current increases for traditional CMOS structures due to the reduction in threshold voltage.

The increase in leakage current due to voltage scaling causes increase in static power dissipation.

Various techniques have been implemented by the researchers to design counters which would consume the lowest power possible.

In this paper, we have presented a design of 4 - bit binary synchronous counter using three different techniques namely CMOS technique, Sleepy transistor technique (STT) and Forced stack technique (FST).

Dsch 3.1 Software Software On 65Nm

The circuit designing and parametric analysis has been carried out using microwind 3.1 and DSCH 3.1 software on 65nm technology.

The height, width, surface area and power consumption in the case of all the three techniques have been measured at three different supply voltages i.e.

It is found that, the power consumed by FST counter and SST counter is much less as compared to power consumed by CMOS counter.

The average power reduction is 44.9 in the case of sleepy transistor technique and the average power reduction is 70.1 in the case of FST as compared to CMOS counter.

Although these techniques are power efficient as compared to CMOS technique but this is on the expense of larger surface area.

Counter designed by these techniques can be useful where low power requirement will be primary concern.